1. Field of the Invention
This invention relates to a slicing level and sampling phase adaptation circuitry, more particularly to a slicing level and sampling phase adaptation circuitry for data recovery systems.
2. Description of the Prior Art
Clock and data recovery circuit is an important component in digital communication systems. The applications include many point-to-point digital communication systems, such as Asynchronous Transfer Mode (ATM), Synchronous Optical Network (SONET), Synchronous Digital Hierarchy (SDH), Fiber Distributed Data Interface (FDDI), Ethernet, Wavelength Division Multiplexing (WDM), Dense Wavelength Division Multiplexing (DWDM), and interface of universal serial bus (USB) between personal computer and external devices.
With the rapid development of multimedia applications and the evolution of manufacturing technology continuing, the clock frequencies on the processing chip was over than 3 GHz. In recent years, the high-speed serial link also encroached on the board level as a standard interface of host computer to reduce the transmission line and power consumption, such as series-ATA and PCI-Express. In the need for more and more data processing, system performance is limited by the transmission problems. Furthermore, the Internet's wide variety of applications needs to transfer huge data rate nowadays. To deal with such throughput demand in this limited Channel has became an inevitable trend.
As the noise of the signal posed by the impact of the increased transfer rate during transmission is increased seriously. Channels interaction (Cross Talk), Electromagnetic Disturbance (EMI), or signal reflections caused by impedance mismatch, the channel itself will generate attenuation of the signals to certain degree. In addition, non-ideal signals transmitting brings shift of frequency and phase . . . and so on. How to achieve high-speed transmission, reduce the limited channel bandwidth and external noise, and then receive the correct data is becoming a formidable problem. Consequently, the issue in data recovery technology for high-speed link transfer is bound with an extremely important role.
FIG. 1 shows a PLL-based CDR (Phase Locked Loop-based Clock and Data Recovery) circuit according to the prior art. Conventional PLL-based CDR circuit including Phase Detector 11, Charge Pump 12, Low-Pass Filter (LPF) 13, and voltage-controlled oscillator (VCO) 14 suffers from device speed limitations with increasing data rates, degradation of on-chip Q for inductors (if an LC-VCO is used), 50 percent duty-cycle problems, data feed through, increased VCO jitter (due to high-VCO gain resulting from supply voltage reduction) and poor performance in the presence of asymmetric jitter. In order to achieve high data rates while maintaining an acceptable performance, reduced-rate architectures are employed. A novel ⅛th-rate PD implementation is reported. A preferred data eye pattern is reasonably symmetric both vertically (in amplitude) and horizontally (in time) as shown in FIG. 2A. In this case, despite that there is jitter and amplitude noise, the best sampling point is at 0.5 UI, and the slicing level is 0 (in the center of the eye.) FIG. 2B shows the case where data eyes have ASE noise. Since the +1 level has much more noise than the −1 level, moving the slicing threshold downward makes the distances from the slicing level to +1 and −1 equal. This will help the system bit error rate performance.
FIG. 3A shows an eye opening with excessive amount of noise according to the prior art. The conventional art may use only two samplers; a fixed sampler in the “middle” of the eye and an adjustable sampler to explore the eye boundary. As long as the two samplers agree on the results; they stay in the eye opening. On the other hand, if the results mismatch, the adjustable sampler enters the clouded area of the eye. This scheme works if the eye opening is reasonably wide and the fixed sampler situated in the center is indeed obtaining the right result. However, if there is too much noise and the center sampler itself is getting the wrong result, the conventional scheme may break as illustrated in FIG. 3B and FIG. 3B.
Conventional clock and data recovery systems assume that the optimal slicing level is in the middle of the vertical height of the eye and the optimal sampling point is halfway between the bit boundaries. However, many non-idealities, including noise, nonlinearities, dispersion, unbalanced rise and fall time, etc, shift the optimal slicing level up or down and sampling point advanced or retarded from the center point.
Due to various effects, including but not limited to amplified spontaneous emission noise, nonlinearity, waveform distortion, unbalanced rise and fall time, etc., in the optical and electrical systems, the optimal slicing level might not be in the center of the eye. The optimal sampling phase might also not be in the middle of the bit. Conventional data recovery systems assuming slicing level's locating in the middle and sampling point in the middle of the bit only reaches sub-optimal performance.
The conventional approach to find the slicing level is to sweep the slicing level and measure the bit error rate. Since it is very unlikely to have a training sequence before data transmission and the real-time bit error rate measurement can introduce humongous area/power penalty, Modern communication systems long for more elegant solutions.